Data packing and unpacking is often necessary when parallel words of a variable width are to be transmitted or recorded utilizing transmission lines or recording/playback equipment which requires data arranged in parallel words having a predetermined width. Another example for using data packing and unpacking is in coding or data compression applications. Known data unpackers utilize parallel-to-serial conversion to convert the packed data into serial data, followed by serial-to-parallel conversion for converting the serial data into parallel words of a variable width, corresponding to the width of the original data words prior to packing. There is a significant disadvantage associated with these prior art data unpackers that a high frequency serial clock is required for the data conversion, whose frequency may exceed the maximum operation frequency of most types of known logic circuits. Generation of the serial clock requires a phase locked loop, whose incorporation decreases the available space on the circuit board, while it increases the number of circuit elements, and therefore also the cost. While for example the well known emitter couple logic (ECL) type logic circuitry may satisfy the high frequency requirement, it is known to have a relatively low packing density, and it requires a relatively high current power supply. Therefore the use of above-indicated known data unpackers is not practical for high packing density, low power and low cost applications. A further disadvantage is that it is difficult to format the data into blocks for synchronization when parallel-to-serial conversion is used because such formatting generally involves inserting additional bits into the serial bit stream, requiring another, higher rate serial clock and the use of high rate first-in, first-out data storage buffers.